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TC59LM836DKB-30,-33,-40 2004-08-27 1/65 rev 1.2 tentative toshiba mos digital integr ated circuit silicon monolithic 288mbits network fcram2 ? 2,097,152-words 4 banks 36-bits description network fcram tm is double data rate fast cycle rand om access memory. TC59LM836DKB is network fcram tm containing 301,989,888 memory cells. tc59l m836dkb is organized as 2,097,152-words 4 banks 36 bits. TC59LM836DKB feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock in put which enables high performance and simple user interf ace coexistence. TC59LM836DKB can operate fast core cycle compared with regular ddr sdram. TC59LM836DKB is suitable for network and other applic ations where large memory density and low power consumption are required. the ou tput driver for network fcram tm is capable of high qua lity fast data transfer under light loading condition. features TC59LM836DKB parameter -30 -33 -40 cl = 4 4.0 ns 4.5 ns 5.0 ns cl = 5 3.5 ns 3.75 ns 4.5 ns t ck clock cycle time (min) cl = 6 3.0 ns 3.33 ns 4.0 ns t rc random read/write cycle time (min) 20.0 ns 22.5 ns 25 ns t rac random access time (max) 20.0 ns 22.5 ns 25 ns i dd1s operating current (single bank) (max) 380 ma 360 ma 340 ma l dd2p power down current (max) 100 ma 95 ma 90 ma l dd6 self-refresh current (max) 15 ma 15 ma 15 ma ? fully synchronous operation ? double data rate (ddr) data input/output are synchronized with both edges of ds / qs. ? differential clock (clk and clk ) inputs cs , fn and all address input signals are sampled on the positive edge of clk. output data (dqs and qs) is aligned to the crossings of clk and clk . ? fast clock cycle time of 3.0 ns minimum clock: 333 mhz maximum data: 666 mbps/pin maximum ? quad independent banks operation ? fast cycle and short latency ? selectable data strobe ? distributed auto-refresh cycle in 3.9 s ? self-refresh ? power down mode ? variable write length control ? write latency = cas latency-1 ? programable cas latency and burst length cas latency = 4, 5, 6 burst length = 2, 4 ? organization: 2,097,152 words 4 banks 36 bits ? power supply voltage v dd : 2.5 v 0.125v v ddq : 1.4 v ~ 1.9 v ? low voltage cmos i/o covered with sstl_18 (half strength driver) and hstl. ? jtag boundary scan ? package: 144ball bga, 1mm 0.8mm ball pitch (p-tfbga144-1119-0.80bz) notice: fcram is trademark of fujitsu limited, japan.
TC59LM836DKB-30,-33,-40 2004-08-27 2/65 rev 1.2 pin names pin name a0~a13 address input ba0, ba1 bank address dq0~dq35 data input/output cs chip select fn function control pd power down control clk, clk clock input lds, uds write data strobe lqs, uqs read data strobe v dd power ( + 2.5 v) v ss ground v ddq power ( + 1.5v / + 1.8 v) (for dq buffer) v ssq ground (for dq buffer) v ref reference voltage nc not connected tms, tdi, tck, tdo boundary scan test access ports
TC59LM836DKB-30,-33,-40 2004-08-27 3/65 rev 1.2 pin assignment (top view) ball pitch=1.0 x 0.8mm 5 a b c d e f g h j k 1 3 6 4 2 l m n p r t u v 11 7 9 12 10 8 v dd v dd q v ss q v dd q v ss q v dd q v ss q v ss v dd v ss v dd v dd q v ss q v dd q v ss q tms v dd q v ss q v ss dq16 dq14 dq12 dq10 lds v ref pd a12 a9 a7 a5 uds dq25 dq23 tck dq21 dq19 v ss dq17 dq15 dq13 dq11 dq9 clk clk a11 a8 a6 a4 dq26 dq24 dq22 v ss dq20 dq18 v dd v dd q v ss q v dd q v ss q v dd q v ss q v ss v dd v ss v dd v dd q v ss q v dd q v ss q v dd v dd q v ss q v dd v dd q v ss q v dd q v ss q v dd q v ss q v ss v dd v ss v dd v dd q v ss q v dd q v ss q v dd v dd q v ss q v ss dq0 dq2 dq4 dq6 dq8 cs a13 ba1 a0 dq27 dq29 dq31 v ss dq33 dq35 v ss dq1 dq3 dq5 dq7 lqs fn nc ba0 a10 uqs dq28 dq30 tdo dq32 dq34 v dd v dd q v ss q v dd q v ss q v dd q v ss q v ss v dd v ss v dd v dd q v ss q v dd q v ss q tdi v dd q v ss q a2 nc a1 a3 0.8mm 1mm : depopulated ball inde x
TC59LM836DKB-30,-33,-40 2004-08-27 4/65 rev 1.2 block diagram note: the TC59LM836DKB configuration is 4 bank of 16384 128 36 of cell array with the dq pins numbered dq0~dq35. dq0~dq17 bank #1 dll clock buffer cl k clk pd to each block command decoder cs fn address buffer control signal generator mode register refresh counter a0~a13 ba0, ba1 bank #0 memory cell array column decoder row decoder burst counter write address latch/ address comparator data control and latch circuit upper address latch read data buffer dq buffer lds lower address latch bank #2 bank #3 write data buffer lqs uds uqs dq18~dq35
TC59LM836DKB-30,-33,-40 2004-08-27 5/65 rev 1.2 absolute maximum ratings symbol parameter rating unit notes v dd power supply voltage ? 0.3~ 3.3 v v ddq power supply voltage (for dq buffer) ? 0.3~v dd + 0.3 v v in input voltage ? 0.3~v dd + 0.3 v v out output and dq pin voltage ? 0.3~v ddq + 0.3 v v ref input reference voltage ? 0.3~v dd + 0.3 v t opr operating temperature (case) 0~85 c t stg storage temperature ? 55~150 c t solder soldering temperature (10 s) 260 c p d power dissipation 2.5 w i out short circuit output current 50 ma caution: conditions outside the limits listed under ?absolute m aximum ratings? may cause permanent damage to the device. the device is not meant to be operated under conditions outside the limits descri bed in the operational section of this specification. exposure to ?absolute maximum ratings? conditions for extended periods may af fect device reliability. recommended dc, ac operating conditions (notes: 1)(t case = 0~85c) symbol parameter min typ. max unit notes v dd power supply voltage 2.375 2.5 2.625 v v ddq power supply voltage (for dq buffer) 1.4 ? 1.9 v v ref reference voltage v ddq /2 95% v ddq /2 v ddq /2 105% v 2 v ih (dc) input dc high voltage v ref + 0.125 ? v ddq + 0.2 v 5 v il (dc) input dc low voltage ? 0.1 ? v ref ? 0.125 v 5 v ick (dc) differential clock dc input voltage ? 0.1 ? v ddq + 0.1 v 10 v id (dc) differential input voltage. clk and clk inputs (dc) 0.4 ? v ddq + 0.2 v 7, 10 v ih (ac) input ac high voltage v ref + 0.2 ? v ddq + 0.2 v 3, 6 v il (ac) input ac low voltage ? 0.1 ? v ref ? 0.2 v 4, 6 v id (ac) differential input voltage. clk and clk inputs (ac) 0.55 ? v ddq + 0.2 v 7, 10 v x (ac) differential ac input cross point voltage v ddq /2 ? 0.125 ? v ddq /2 + 0.125 v 8, 10 v iso (ac) differential clock ac middle level v ddq /2 ? 0.125 ? v ddq /2 + 0.125 v 9, 10
TC59LM836DKB-30,-33,-40 2004-08-27 6/65 rev 1.2 note: (1) all voltages referenced to v ss , v ssq . (2) v ref is expected to track variations in v ddq dc level of the transmitting device. peak to peak ac noise on v ref may not exceed 2% v ref (dc). (3) overshoot limit: v ih (max) = v ddq + 0.7 v with a pulse width 5 ns. (4) undershoot limit: v il (min) = ? 0.7 v with a pulse width 5 ns. (5) v ih (dc) and v il (dc) are levels to mainta in the current logic state. (6) v ih (ac) and v il (ac) are levels to change to the new logic state. (7) v id is differential voltage of clk input level and clk input level. (8) the value of v x (ac) is expected to equal v ddq /2 of the transmitting device. (9) v iso means {v ick (clk) + v ick ( clk )} /2 (10) refer to the figure below. (11) in the case of external term ination, vtt (termination voltage) should be gone in the range of v ref (dc) 0.04 v. capacitance (v dd = 2.5v , v ddq = 1.8 v, f = 1 mhz, ta = 25c) symbol parameter min max delta unit c in input pin capacitance 1.5 3.0 0.25 pf c inc clock pin (clk, clk ) capacitance 1.5 3.0 0.25 pf c i/o dq, lds, uds, lqs, uqs capacitance 2.5 3.5 0.5 pf c nc nc pin capacitance ? 1.5 ? pf note: these parameters are periodi cally sampled and not 100% tested. v iso ( min ) v iso ( max ) v ick v ick v x v x v x v x v x v ick v ick cl k clk v ss |v id (ac)| 0 v differential v iso v ss v id (ac)
TC59LM836DKB-30,-33,-40 2004-08-27 7/65 rev 1.2 recommended dc operating conditions (v dd = 2.5 v 0.125 v, v ddq = 1.4 v ~ 1.9 v, t case = 0 ~ 85c) max symbol parameter -30 -33 -40 unit notes i dd1s operating current one bank read or write operation ; t ck = min; i rc = min, i out = 0ma ; burst length = 4, cas latency = 6, free running qs mode ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq , address inputs change up to 2 times during minimum i rc , read data change twice per clock cycle 380 360 340 1, 2 i dd2n standby current all banks: inactive state ; t ck = min, cs = v ih , pd = v ih ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; other input signals change one time during 4 t ck , dq and ds inputs change twice per clock cycle 120 110 100 1, 2 i dd2p standby (power down) current all banks: inactive state ; t ck = min, pd = v il (power down) ; cas latency = 6, free running qs mode ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; other input signals change one time during 4 t ck , dq and ds inputs are floating (v ddq /2) 100 95 90 1, 2 i dd4w write operating current (4banks) 4 bank interleaved continuous burst write operation ; t ck = min, i rc = min ; burst length = 4, cas latency = 6, free running qs mode ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; address inputs change once per clock cycle, dq and ds inputs change twice per clock cycle 850 800 750 1, 2 i dd4r read operating current (4banks) 4 bank interleaved continuous burst read operation ; t ck = min, i rc = min, i out = 0ma ; burst length = 4, cas latency = 6, free running qs mode ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; address inputs change once per clock cycle, read data change twice per clock cycle 850 800 750 1, 2 i dd5b burst auto refresh current refresh command at every i refc interval ; t ck = min; i refc = min ; cas latency = 6, free running qs mode ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq , address inputs change up to 2 times during minimum i refc , dq and ds inputs change twice per clock cycle 380 360 340 1, 2, 3 i dd6 self-refresh current pd = 0.2 v ; other input signals are floating (v ddq /2), dq and ds inputs are floating (v ddq /2) 15 15 15 ma 2 notes: 1. these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck , t rc and i rc . 2. these parameters define the current between v dd and v ss . 3. i dd5b is specified under burst refresh condition. actual system should use distributed refresh that meet to t refi specification.
TC59LM836DKB-30,-33,-40 2004-08-27 8/65 rev 1.2 recommended dc operating conditions (continued) (v dd = 2.5 v 0.125 v, v ddq = 1.4 v ~ 1.9 v, t case = 0 ~ 85c) symbol parameter min max unit notes i li input leakage current ( 0 v v in v ddq , all other pins not under test = 0 v) ? 5 5 a i lo output leakage current (output disabled, 0 v v out v ddq ) ? 5 5 a i ref v ref current ? 5 5 a i oh (dc) v oh = 1.420 v ? 5.6 ? i ol (dc) normal output driver v ol = 0.280 v 5.6 ? i oh (dc) v oh = 1.420 v ? 9.8 ? i ol (dc) strong output driver v ol = 0.280 v 9.8 ? i oh (dc) v oh = 1.420 v ? 2.8 ? i ol (dc) weak output driver output dc current (v ddq = 1.7v~1.9v) v ol = 0.280 v 2.8 ma 1 i oh (dc) v oh = v ddq ? 0.4v ? 4 ? i ol (dc) normal output driver v ol = 0.4v 4 ? i oh (dc) v oh = v ddq ? 0.4v ? 8 ? i ol (dc) strong output driver v ol = 0.4v 8 ? i oh (dc) not defined ? ? i ol (dc) weak output driver output dc current (v ddq = 1.4v~1.6v) not defined ? ? ma 1 notes: 1. refer to output driver characteristics for the deta il. output driver strength is selected by extended mode register.
TC59LM836DKB-30,-33,-40 2004-08-27 9/65 rev 1.2 ac characteristics and operating conditions (notes: 1, 2) ( v dd = 2.5 0.125v, v ddq = 1.4 1.9v, t case = 0 85c) -30 -33 -40 symbol parameter min max min max min max unit notes t rc random cycle time 20.0 ? 22.5 ? 25 ? 3 c l = 4 4.0 5.0 4.5 7.5 5.0 7.5 3 c l = 5 3.5 5.0 3.75 7.5 4.5 7.5 3 t ck clock cycle time c l = 6 3.0 5.0 3.33 7.5 4.0 7.5 3 t rac random access time ? 20.0 ? 22.5 ? 25 3 t ch clock high time 0.45 t ck ? 0.45 t ck ? 0.45 t ck ? 3 t cl clock low time 0.45 t ck ? 0.45 t ck ? 0.45 t ck ? 3 t ckqs qs access time from clk ? 0.45 0.45 ? 0.45 0.45 ? 0.5 0.5 3, 8,10 t qsq data output skew from qs ? 0.2 ? 0.25 ? 0.3 t qsqa data output skew from qs to all dq ? 0.3 ? 0.35 ? 0.4 t ac data access time from clk ? 0.5 0.5 ? 0.5 0. 5 ? 0.6 0.6 3, 8,10 t oh data output hold time from clk ? 0.5 0.5 ? 0.5 0.5 ? 0.6 0.6 3, 8 t hp clk half period (minimum of actual t ch , t cl ) min(t ch , t cl ) ? min(t ch , t cl ) ? min(t ch , t cl ) ? 3 t qsp qs (read) pulse width t hp ? t qhs ? t hp ? t qhs ? t hp ? t qhs ? 4, 8 t qsqv data output valid time from qs t hp ? t qhs ? t hp ? t qhs ? t hp ? t qhs ? 4, 8 t qhs dq, qs hold skew factor ? 0.055 t ck + 0.17 ? 0.055 t ck + 0.17 ? 0.055 t ck + 0.17 t dqss ds (write) low to high setup time 0.8 t ck 1.2 t ck 0.8 t ck 1.2 t ck 0.8 t ck 1.2 t ck 3 t dspre ds (write) preamble pulse width 0.4 t ck ? 0.4 t ck ? 0.4 t ck ? 4 t dspres ds first input setup time 0 ? 0 ? 0 ? 3 t dspreh ds first low input hold time 0.3 t ck ? 0.3 t ck ? 0.3 t ck ? 3 t dsp ds high or low input pulse width 0.45 t ck 0.55 t ck 0.45 t ck 0.55 t ck 0.45 t ck 0.55 t ck 4 c l = 4 0.75 ? 0.8 ? 1.0 ? 3, 4 c l = 5 0.75 ? 0.8 ? 1.0 ? 3, 4 t dss ds input falling edge to clock setup time c l = 6 0.75 ? 0.8 ? 1.0 ? 3, 4 t dspst ds (write) postamble pulse width 0.45 t ck ? 0.45 t ck ? 0.45 t ck ? 4 c l = 4 0.75 ? 0.8 ? 1.0 ? 3, 4 c l = 5 0.75 ? 0.8 ? 1.0 ? 3, 4 t dspsth ds (write) postamble hold time c l = 6 0.75 ? 0.8 ? 1.0 ? 3, 4 t dssk uds ? lds skew ? 0.4 t ck 0.4 t ck ? 0.4 t ck 0.4 t ck ? 0.4 t ck 0.4 t ck t ds data input setup time from ds 0.3 ? 0.35 ? 0.4 ? 4, 11 t dh data input hold time from ds 0.3 ? 0.35 ? 0.4 ? 4, 11 t is command/address input setup time 0.6 ? 0.6 ? 0.7 ? 3 t ih command/address input hold time 0.6 ? 0.6 ? 0.7 ? ns 3
TC59LM836DKB-30,-33,-40 2004-08-27 10/65 rev 1.2 ac characteristics and operating conditions (notes: 1, 2) (continued) -30 -33 -40 symbol parameter min max min max min max unit notes t lz data-out low impedance time from clk ? 0.5 ? ? 0.5 ? ? 0.6 ? 3, 6, 8 t hz data-out high impedance time from clk ? 0.5 ? 0.5 ? 0.6 3, 7, 8 t qpdh last output to pd high hold time 0 ? 0 ? 0 ? t pdex power down exit time 0.6 ? 0.6 ? 0.7 ? 3 t t input transition time 0.1 1 0.1 1 0.1 1 t fpdl pd low input window for self-refresh entry ? 0.5 t ck 5 ? 0.5 t ck 5 ? 0.5 t ck 5 ns 3 t refi auto-refresh average interval 0.4 3.9 0.4 3.9 0.4 3.9 5 t pause pause time after power-up 200 ? 200 ? 200 ? s c l = 4 5 ? 5 ? 5 ? c l = 5 6 ? 6 ? 6 ? i rc random read/write cycle time (applicable to same bank) c l = 6 7 ? 7 ? 7 ? i rcd rda/wra to lal command input delay (applicable to same bank) 1 1 1 1 1 1 c l = 4 4 ? 4 ? 4 ? c l = 5 5 ? 5 ? 5 ? i ras lal to rda/wra command input delay (applicable to same bank) c l = 6 6 ? 6 ? 6 ? i rbd random bank access delay (applicable to other bank) 2 ? 2 ? 2 ? b l = 2 2 ? 2 ? 2 ? i rwd lal following rda to wra delay (applicable to other bank) b l = 4 3 ? 3 ? 3 ? i wrd lal following wra to rda delay (applicable to other bank) 1 ? 1 ? 1 ? c l = 4 7 ? 7 ? 7 ? c l = 5 7 ? 7 ? 7 ? i rsc mode register set cycle time c l = 6 7 ? 7 ? 7 ? i pd pd low to inactive state of input buffer ? 2 ? 2 ? 2 i pda pd high to active state of input buffer 1 ? 1 ? 1 ? c l = 4 19 ? 19 ? 19 ? c l = 5 23 ? 23 ? 23 ? i pdv power down mode valid from ref command c l = 6 25 ? 25 ? 25 ? c l = 4 19 ? 19 ? 19 ? c l = 5 23 ? 23 ? 23 ? i refc auto-refresh cycle time c l = 6 25 ? 25 ? 25 ? i ckd ref command to clock input disable at self-refresh entry i refc ? i refc ? i refc ? i lock dll lock-on time (applicable to rda command) 200 ? 200 ? 200 ? cycle
TC59LM836DKB-30,-33,-40 2004-08-27 11/65 rev 1.2 ac test conditions symbol parameter value unit notes v ih (min) input high voltage (minimum) v ref + 0.2 v v il (max) input low voltage (maximum) v ref ? 0.2 v v ref input reference voltage v ddq /2 v v tt termination voltage v ref v v swing input signal peak to peak swing 0.8 v vr differential clock input reference level v x (ac) v v id (ac) input differential voltage 1.0 v slew input signal minimum slew rate 2.5 v/ns v otr output timing measurement reference voltage v ddq /2 v 9 note: (1) transition times ar e measured between v ih min (dc) and v il max (dc). transition (rise and fall) of in put signals have a fixed slope. (2) if the result of nominal calculation with regard to t ck contains more than one de cimal place, the result is rounded up to the nearest decimal place. (i.e., t dqss = 0.8 t ck , t ck = 3.3 ns, 0.8 3.3 ns = 2.64 ns is rounded up to 2.7 ns.) (3) these parameters are measured fr om the differential clock (clk and clk ) ac cross point. (4) these parameters are measured from si gnal transition point of ds crossing v ref level. (5) the t refi (max) applies to equally distributed refresh method. the t refi (min) applies to both burst refresh meth od and distributed refresh method. in such case, the average interval of eight consecutive auto-refresh commands has to be more than 400 ns always. in other words, the number of auto-refresh cycles which can be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. (6) low impedance state is specified at v ddq /2 0.1 v from steady state. (7) high impedance state is specified wh ere output buffer is no longer driven. (8) these parameters depend on the clock jitter. these parameters are meas ured at stable clock. (9) output timing is measured by using normal driver strength at v ddq = 1.7 v 1.9 v. output timing is measured by using strong driver strength at v ddq = 1.4 v~1.6 v. (10) these parameters are measured at t ck = minimum 6.0ns. when t ck is longer than 6.0ns, these parameters are specified as below for all speed version. t ckqs (min/max) = ? 0.6ns / 0.6ns, t ac (min/max) = ? 0.65ns / 0.65ns (11) these parameters are measured at v ddq = 1.7 v 1.9 v. both t ds and t dh at v ddq = 1.4 v 1.6 v are specified as below for all speed version. t ds (min) = 0.4 ns , t dh (min) = 0.4 ns slew = (v ih min (ac) ? v il max (ac))/ ? t v ih min (ac) ? t v ref v il max (ac) v swing ? t v ss v ddq ac test load measurement point output v tt 25 ?
TC59LM836DKB-30,-33,-40 2004-08-27 12/65 rev 1.2 power up sequence (1) as for pd , being maintained by the low state ( 0.2 v) is desirable before a power-supply injection. (2) apply v dd before or at the same time as v ddq . (3) apply v ddq before or at the same time as v ref . (4) start clock (clk, clk ) and maintain stable condition for 200 s (min). (5) after stable power and clock, apply desl and take pd =h. (6) issue emrs to enable dll and to define driv er strength and data strobe type. (note: 1) (7) issue mrs for set cas latency (cl), burst type (bt), and burst length (bl). (note: 1) (8) issue two or more auto-refresh commands (note: 1). (9) ready for normal operation after 200 clocks from extended mode register programming. notes: (1) sequence 6, 7 and 8 can be issued in random order. (2) l = logic low, h = logic high (3) dq output is hi-z state during power upsequence. command clk address v dd v ddq v ref ds l/uqs (free running mode) clk pd 2.5v ( typ ) 1.5v or 1.8v ( typ ) 1/2 v ddq (typ) 200us ( min ) t pdex l pda l rsc l rsc l refc l refc l lock = 200clock cycle(min) desl rda mrs desl rda mrs desl wra ref desl wra ref desl op-code emrs op-code mrs l/uqs (uni-qs mode) emrs mrs auto refresh cycle normal operation low dq (input)
TC59LM836DKB-30,-33,-40 2004-08-27 13/65 rev 1.2 timing diagrams input timing timing of the clk, t t t ck clk v ih v il v ih v il t cl t ch t t v ih (ac) v il (ac) clk clk clk v x v x v x v id (ac) clk t ih t is t ih t ck t cl t ch cs cl k clk refer to the command truth table. t ck 1st 2nd t is t ih t is t ih 1st 2nd t ih t is t ih ua, ba la t is t is fn a0~a13 ba0, ba1 l/uds command and address data dqn (input) t ds t dh t ds t dh t ds t dh t ds t dh dqm (input)
TC59LM836DKB-30,-33,-40 2004-08-27 14/65 rev 1.2 read timing (burst length = 4) unidirectional ds/qs mode clk clk inpu t (control & addresses) ds (input) lal (after rda) t is t ih t ch t cl t ck desl lqs (output) ldq (output) cas latency = 4 low hi-z t qsq t ckqs t ckqs t qsp t qsp t ckqs t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 low uqs (output) udq (output) low hi-z t ckqs t qsp t qsp t ckqs t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 low t qsq a t qsq a t qsq a t qsq a t qsq a t qsq a lqs (output) ldq (output) cas latency = 5 low hi-z t qsq t ckqs t ckqs t qsp t qsp t ckqs t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 low uqs (output) udq (output) low hi-z t ckqs t qsp t qsp t ckqs t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 low t qsq a t qsq a t qsq a t qsq a t qsq a t qsq a
TC59LM836DKB-30,-33,-40 2004-08-27 15/65 rev 1.2 read timing (burst length = 4) unidirectional ds/qs mode clk clk inpu t (control & addresses) ds (input) lal (after rda) t is t ih t ch t cl t ck desl lqs (output) ldq (output) cas latency = 6 low hi-z t qsq t ckqs t ckqs t qsp t qsp t ckqs t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 low uqs (output) udq (output) low hi-z t ckqs t qsp t qsp t ckqs t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 low t qsq a t qsq a t qsq a t qsq a t qsq a t qsq a note: dq0 to dq35 are aligned with qs. the correspondence of lqs, uqs to dq. lqs dq0~dq17 uqs dq18~dq35
TC59LM836DKB-30,-33,-40 2004-08-27 16/65 rev 1.2 read timing (burst length = 4) unidirectional ds/free running qs mode clk clk inpu t (control & addresses) ds (input) lal (after rda) t is t ih t ch t cl t ck desl lqs (output) ldq (output) cas latency = 4 hi-z t qsq t ckqs t ckqs t qsp t qsp t ckqs t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 uqs (output) udq (output) hi-z t ckqs t qsp t qsp t ckqs t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 t qsq a t qsq a t qsq a t qsq a t qsq a t qsq a lqs (output) ldq (output) cas latency = 5 hi-z t qsq t ckqs t ckqs t qsp t qsp t ckqs t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 uqs (output) udq (output) hi-z t ckqs t qsp t qsp t ckqs t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 t qsq a t qsq a t qsq a t qsq a t qsq a t qsq a
TC59LM836DKB-30,-33,-40 2004-08-27 17/65 rev 1.2 read timing (burst length = 4) unidirectional ds/free running qs mode clk clk inpu t (control & addresses) ds (input) lal (after rda) t is t ih t ch t cl t ck desl lqs (output) ldq (output) cas latency = 6 hi-z t qsq t ckqs t ckqs t qsp t qsp t ckqs t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 uqs (output) udq (output) hi-z t ckqs t qsp t qsp t ckqs t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 t qsq a t qsq a t qsq a t qsq a t qsq a t qsq a note: dq0 to dq35 are aligned with qs. the correspondence of lqs, uqs to dq. lqs dq0~dq17 uqs dq18~dq35
TC59LM836DKB-30,-33,-40 2004-08-27 18/65 rev 1.2 write timing (burst length = 4) unidirectional ds/qs mode, unidirectional ds/free running qs mode dq (input) l/uds (input) dq (input) cas latency = 5 l/uds (input) cas latency = 4 t dspre t ds t dh d0 d1 t ds t dh d2 d3 t ds t dh t dss t dqss t dspreh t dsp t dsp t ds preamble postamble t dsp t dqss t dspres t dspst t dspsth t dh d0 d1 t ds t dh d2 d3 t ds t dh t dss t dqss t dspreh t dsp t dsp preamble postamble t dsp t dss t dspres t dspst t dss t dspsth t dqss cl k clk inpu t (control & addresses) lal (after wra) t is t ih t ch t cl t ck t dspre l/uds (input) dq (input) cas latency = 6 t dspre t dss t dspreh t dsp t dsp t ds preamble postamble t dsp t dqss t dspres t dspst t dspsth t dh d0 d1 t ds t dh d2 d3 t ds t dh t dss t dqss l/uqs (uni-qs) l/uqs (free runninig) low desl note: dq0 to dq35 are sampled at both edges of ds. the correspondence of lds, uds to dq. lds dq0~dq17 uds dq18~dq35
TC59LM836DKB-30,-33,-40 2004-08-27 19/65 rev 1.2 t refi , t pause , i xxxx timing cl k clk input (control & addresses) command t is t ih note: ?i xxxx ? means ?i rc ?, ?i rcd ?, ?i ras ?, etc. t refi , t pause , i xxxx command t is t ih
TC59LM836DKB-30,-33,-40 2004-08-27 20/65 rev 1.2 function truth table (notes: 1, 2, 3) command truth table (notes: 4) ? the first command symbol function cs fn ba1~ba0 a13~a10 a9~a8 a7 a6~a0 desl device deselect h rda read with auto-close l h ba ua ua ua ua wra write with auto-close l l ba ua ua ua ua ? the second command (the next clock of rda or wra command) symbol function cs fn ba1~ ba0 a13~ a12 a11~ a10 a9 a8 a7 a6~a0 lal lower address latch h v la ref auto-refresh l mrs mode register set l v l l l l v v notes: 1. l = logic low, h = logic high, = either l or h, v = valid (specified value), ba = bank address, ua = upper address, la = lower address 2. all commands are assumed to issue at a valid state. 3. all inputs for command (excluding selfx and pdex) are la tched on the crossing point of differential clock input where clk goes to high. 4. operation mode is decided by the combination of 1st command and 2nd command. refer to ?state diagram? and the command table below. read command table command (symbol) cs fn ba1~ba0 a13~a10 a9~a8 a7 a6~a0 notes rda (1st) l h ba ua ua ua ua lal (2nd) h la write command table command(symbol) cs fn ba1~ ba0 a13 a12 a11 a10 a9~a8 a7 a6~a0 wra (1st) l l ba ua ua ua ua ua ua ua lal (2nd) h vw0 vw1 la notes: 5. a13~ a12 are used for variable write length (vw) control at write operation. vw truth table burst length function vw0 vw1 write all words l bl=2 write first one word h reserved l l write all words h l write first two words l h bl=4 write first one word h h
TC59LM836DKB-30,-33,-40 2004-08-27 21/65 rev 1.2 function truth table (continued) mode register set command table command (symbol) cs fn ba1~ba0 a13~a9 a8 a7 a6~a0 notes rda (1st) l h mrs (2nd) l v v v v v 6 notes: 6. refer to ?mode register table?. auto-refresh command table pd function command (symbol) current state n ? 1n cs fn ba1~ba0 a13~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l auto-refresh ref (2nd) active h h l self-refresh command table pd function command (symbol) current state n ? 1n cs fn ba1~ba0 a13~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l self-refresh entry ref (2nd) active h l l 7, 8 self-refresh continue ? self-refresh l l self-refresh exit selfx self-refresh l h h 9 power down table pd function command (symbol) current state n ? 1n cs fn ba1~ba0 a13~a9 a8 a7 a6~a0 notes power down entry pden standby h l h 8 power down continue ? power down l l power down exit pdex power down l h h 9 notes: 7. pd has to be brought to low within t fpdl from ref command. 8. pd should be brought to low after dq?s state turned high impedance. 9. when pd is brought to high from low, this function is executed asynchronously.
TC59LM836DKB-30,-33,-40 2004-08-27 22/65 rev 1.2 function truth table (continued) pd current state n ? 1 n cs fn address command action notes h h h desl nop h h l h ba, ua rda row activate for read h h l l ba, ua wra row activate for write h l h pden power down entry 10 h l l ? illegal idle l ? refer to power down state h h h la lal begin read h h l op-code mrs/emrs access to mode register h l h pden illegal h l l mrs/emrs illegal row active for read l ? invalid h h h la lal begin write h h l ref auto-refresh h l h pden illegal h l l ref (self) self-refresh entry row active for write l ? invalid h h h desl continue burst read to end h h l h ba, ua rda illegal 11 h h l l ba, ua wra illegal 11 h l h pden illegal h l l ? illegal read l ? invalid h h h desl data write&continue burst write to end h h l h ba, ua rda illegal 11 h h l l ba, ua wra illegal 11 h l h pden illegal h l l ? illegal write l ? invalid h h h desl nop idle after i refc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden self-refresh entry 12 h l l ? illegal auto-refreshing l ? refer to self-refreshing state h h h desl nop idle after i rsc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden illegal h l l ? illegal mode register accessing l ? invalid h ? invalid l l ? maintain power down mode l h h pdex exit power down mode idle after t pdex power down l h l ? illegal h ? invalid l l ? maintain self-refresh l h h selfx exit self-refresh idle after i refc self-refreshing l h l ? illegal notes: 10. illegal if any bank is not idle. 11. illegal to bank in specified stat es; function may be legal in the bank inidicated by bank address (ba). 12. illegal if t fpdl is not satisfied.
TC59LM836DKB-30,-33,-40 2004-08-27 23/65 rev 1.2 mode register table regular mode register (notes: 1) address ba1 * 1 ba0 * 1 a13~a8 a7 * 3 a6~a4 a3 a2~a0 register 0 0 0 te cl bt bl a7 test mode (te) a3 burst type (bt) 0 regular (default) 0 sequential 1 test mode entry 1 interleave a6 a5 a4 cas latency (cl) a2 a1 a0 burst length (bl) 0 0 reserved * 2 0 0 0 reserved * 2 0 1 0 reserved * 2 0 0 1 2 0 1 1 reserved * 2 0 1 0 4 1 0 0 4 0 1 1 1 0 1 5 1 reserved * 2 1 1 0 6 1 1 1 reserved * 2 extended mode register (notes: 4) address ba1 * 4 ba0 * 4 a13~a7 a6~a5 a4~a3 a2~a1 a0 * 5 register 0 1 0 ss dic (qs) dic (dq) ds qs dq a6 a5 strobe select a4 a3 a2 a1 output drive impedance control (dic) 0 0 reserved * 2 0 0 0 0 normal output driver 0 1 reserved * 2 0 1 0 1 strong output driver 1 0 unidirectional ds/qs 1 0 1 0 weak output driver 1 1 unidirectional ds/free running qs 1111 reserved a0 dll switch (ds) 0 dll enable 1 dll disable notes: 1. regular mode register is chosen using the combination of ba0 = 0 and ba1 = 0. 2. ?reserved? places in regular mode register should not be set. 3. a7 in regular mode register must be set to ?0? (low state). because test mode is specific mode for supplier. 4. extended mode register is chosen using the combination of ba0 = 1 and ba1 = 0. 5. a0 in extended mode register must be set to "0" to enable dll for normal operation.
TC59LM836DKB-30,-33,-40 2004-08-27 24/65 rev 1.2 state diagram standby (idle) self- refresh power down pden ( pd = l) pdex ( pd = h) selfx ( pd = h) mode register auto- refresh active active (restore) read write (buffer) pd = l pd = h wra rda mrs ref command input lal a utomatic return the second command at active state must be issued 1 clock after rda or wra command input. lal
TC59LM836DKB-30,-33,-40 2004-08-27 25/65 rev 1.2 timing diagrams single bank read timing (cl = 4) cl k clk low ds (input) dq (output) bl = 2 i rc = 5 c y cles hi-z q0 q1 cl = 4 command i rc = = 5 c y cles address ua la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle i ras = 4 cycles bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) cl = = 4 low ds (input) dq (output) bl = 4 hi-z q0 q1 cl = 4 qs (output) cl = = 4 q2 q3 q2 q3 ds (input) dq (output) bl = 2 hi-z q0 q1 cl = 4 unidirectional ds/free running qs mode qs (output) cl = = 4 ds (input) dq (output) bl = 4 hi-z q0 q1 cl = 4 qs (output) cl = = 4 q2 q3 q2 q3 rda ua #0
TC59LM836DKB-30,-33,-40 2004-08-27 26/65 rev 1.2 single bank read timing (cl = 5) i rc = = 2 hi-z q0 q1 cl = 5 command i rc = = 5 c y cles i rcd = 1 c y cle i ras = = = 1 c y cle bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) cl = = 4 hi-z q0 q1 cl = 5 qs (output) cl = = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) desl hi-z q0 q1 cl = 5 cl = = 5 cl =
TC59LM836DKB-30,-33,-40 2004-08-27 27/65 rev 1.2 single bank read timing (cl = 6) i rc = 7 cycles clk clk low ds (input) dq (output) bl = 2 hi-z q0 q1 cl = 6 command i rc = = 6 cycles i rcd = 1 cycle i ras = 6 cycles i rcd = 1 cycle i rcd = 1 cycle bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) cl = 6 q0 q1 low ds (input) dq (output) bl = 4 hi-z q0 q1 cl = 6 qs (output) cl = 6 q0 q1 q2 q3 q2 ds (input) dq (output) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) desl hi-z q0 q1 cl = 6 cl = 6 q0 q1 hi-z q0 q1 cl = 6 cl = 6 q0 q1 q2 q3 q2 lal
TC59LM836DKB-30,-33,-40 2004-08-27 28/65 rev 1.2 single bank write timing (cl = 4) cl k clk low ds (input) dq (input) bl = 2 i rc = 5 cycles wl = 3 command i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal desl wra lal wra lal desl desl i rc = 5 cycles address ua la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle i ras = 4 cycles bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) wl = = 3 low ds (input) dq (input) bl = 4 d0 d1 wl = 3 qs (output) wl = = 3 d2 d3 ds (input) dq (input) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (input) qs (output) d0 d1 d0 d1 d0 d1 d2 d3 d0 d1 d2 wl = 3 wl = = 3 d0 d1 d0 d1 d0 d1 wl = 3 wl = = 3 d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 bl = 4 wra ua #0 d3 d3
TC59LM836DKB-30,-33,-40 2004-08-27 29/65 rev 1.2 single bank write timing (cl = 5) i rc = = 2 wl = 4 command i rc = = 5 cycles i rcd = 1 cycle i ras = 5 cycles i rcd = 1 cycle i rcd = 1 cycle bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) wl = = 4 qs (output) ds (input) dq (input) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (input) bl = 4 qs (output) desl d0 d1 d0 d1 wl = 4 wl = = 4 wl = = 4 wl =
TC59LM836DKB-30,-33,-40 2004-08-27 30/65 rev 1.2 single bank write timing (cl = 6) i r c = 7 c y cles clk clk low ds (input) dq (input) bl = 2 wl = 5 command i r c = = 6 c y cles i rcd = 1 c y cle i ras = = = = = 4 qs (output) ds (input) dq (input) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (input) bl = 4 qs (output) desl lal d0 d1 wl = 5 wl = = 5 wl = = 5 wl =
TC59LM836DKB-30,-33,-40 2004-08-27 31/65 rev 1.2 single bank read-write timing (cl = 4) cl k clk low ds (input) dq bl = 2 i rc = 5 cycles hi-z q0 q1 cl = 4 command i rc = = 5 c y cles address ua la ua la ua la bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) wl = = 4 low ds (input) dq bl = 4 hi-z q0 q1 cl = 4 qs (output) wl = = 4 q2 q3 d2 d3 ds (input) dq bl = 2 hi-z q0 q1 cl = 4 unidirectional ds/free running qs mode qs (output) wl = = 4 ds (input) dq bl = 4 hi-z q0 q1 cl = 4 qs (output) wl = = 4 q2 q3 d0 d1 d2 d3 read data write data wra ua #0
TC59LM836DKB-30,-33,-40 2004-08-27 32/65 rev 1.2 single bank read-write timing (cl = 5) cl k clk ds (input) dq bl = 2 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 desl address bank add. unidirectional ds/qs mode qs (output) ds (input) dq bl = 4 qs (output) ds (input) dq bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq bl = 4 qs (output) i rc = 6 cycles low hi-z q0 q1 cl = 5 i rc = 6 cycles rda lal rda lal wra lal desl ua la ua la ua la #0 #0 #0 wl = 4 d0 d1 low hi-z q0 q1 cl = 5 q2 q3 d0 d1 d2 d3 desl hi-z q0 q1 cl = 5 d0 d1 hi-z q0 q1 cl = 5 q2 q3 d0 d1 d2 d3 wl = 4 wl = 4 wl = 4 read data write data
TC59LM836DKB-30,-33,-40 2004-08-27 33/65 rev 1.2 single bank read-write timing (cl = 6) i rc = 7 cycles clk clk low ds (input) dq bl = 2 hi-z q0 q1 cl = 6 command i rc = 7 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda rda lal wra lal desl address ua la ua la ua la bank add. #0 #0 #0 unidirectional ds/qs mode qs (output) wl = = 4 hi-z q0 q1 cl = 6 qs (output) q2 q3 ds (input) dq bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) desl hi-z q0 q1 cl = 6 d0 d1 hi-z q0 q1 cl = 6 q2 q3 lal wl = = =
TC59LM836DKB-30,-33,-40 2004-08-27 34/65 rev 1.2 multiple bank read timing (cl = 4) rda ua bank "b" clk clk low ds (input) dq (output) bl = 2 i rbd = 2 cycles hi-z qa0 qa1 cl = 4 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal rda rda lal rda lal address ua la ua la ua la bank add. bank "a" unidirectional ds/qs mode qs (output) cl = 4 ds (input) bl = 4 rda lal desl i rbd = 2 cycles rda lal rda i rbd = 2 cycles i rbd = 2 cycles lal rda lal ua la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1 i rbd = 2 cycles dq (output) hi-z qs (output) ds (input) dq (output) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) low cl = 4 cl = 4 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 cl = 4 cl = 4 cl = 4 cl = 4 note: l rc to the same bank must be satisfied. hi-z qa0 qa1 qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1 hi-z qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 la
TC59LM836DKB-30,-33,-40 2004-08-27 35/65 rev 1.2 multiple bank read timing (cl = 5) cl k clk ds (input) dq (output) bl = 2 hi-z cl = 5 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal rda lal rda address ua la ua la ua bank add. bank "a" unidirectional ds/qs mode qs (output) cl = = 4 hi-z qs (output) ds (input) dq (output) bl = 2 hi-z unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 hi-z qs (output) rda lal lal rda lal rda lal rda ua la la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" i rc (bank"a") = 6 cycles i rc (bank"b") = 6 cycles low low cl = 5 cl = = 5 cl = = 5 cl = = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles lal la qa0qa1qa2qa3qb0qb1qb2qb3 qa0 qa1 qa2 qa3 qb0qb1qb2 qa0qa1 qb0qb1 qa0 qa1 qb0qb1 qa0qa1 qa0qa1qa2qa3qb0qb1qb2qb3 qa0 qa1 qa2 qa3 qb0qb1qb2 qb0qb1 qa0 qa1 qb0qb1
TC59LM836DKB-30,-33,-40 2004-08-27 36/65 rev 1.2 multiple bank read timing (cl = 6) clk clk low ds (input) dq (output) bl = 2 hi-z qa0 qa1 cl = 6 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal rda lal address ua la ua la ua bank add. bank "a" unidirectional ds/qs mode qs (output) cl = 6 ds (input) dq (output) bl = 4 hi-z qs (output) ds (input) dq (output) bl = 2 unidirectional ds/free running qs mode qs (output) ds (input) dq (output) bl = 4 qs (output) rda lal lal rda lal rda lal ua la la ua la ua la bank "b" bank "b" bank "c" bank "d" i rc (bank"a") = 7 cycles i rc (bank"b") = 7 cycles qb0 qa0 qa1 low cl = 6 cl = 6 cl = 6 cl = 6 cl = 6 cl = 6 bank "a" desl i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles rda ua bank "a" hi-z hi-z rda qb1 qa0qa1qa2 qa0qa1 qb0qb1 qa0qa1 qa0qa1qa2qa3qb0qb1qb2qb3 qa0qa1qa2 qa0qa1qa2qa3qb0qb1qb2qb3 note: l rc to the same bank must be satisfied.
TC59LM836DKB-30,-33,-40 2004-08-27 37/65 rev 1.2 multiple bank write timing (cl = 4) clk clk low ds (input) dq (input) bl = 2 wl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal wra wra lal wra lal address ua la ua la ua la bank add. bank "a" unidirectional ds/qs mode qs (output) wl = 3 ds (input) dq (input) bl = 4 qs (output) unidirectional ds/free running qs mode wra lal desl wra lal wra lal wra lal ua la ua la ua la ua la bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles db0 db1 da0 da1 db0 db1 dc0 dc1 low da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 dc2 dc3 note: l rc to the same bank must be satisfied. i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 dd0 dd1 wl = 3 wl = 3 dd0 dd1 ds (input) dq (input) bl = 2 wl = 3 qs (output) wl = 3 ds (input) dq (input) bl = 4 qs (output) db0 db1 da0 da1 db0 db1 dc0 dc1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 dc2 dc3 da0 da1 dd0 dd1 wl = 3 wl = 3 dd0 dd1 wra ua bank "b"
TC59LM836DKB-30,-33,-40 2004-08-27 38/65 rev 1.2 multiple bank write timing (cl = 5) clk clk low ds (input) dq (input) bl = 2 wl = 4 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal wra lal wra address ua la ua la ua la bank add. bank "a" unidirectional ds/qs mode qs (output) wl = = 4 qs (output) unidirectional ds/free running qs mode wra lal lal wra lal wra lal wra ua la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 6 cycles i rc (bank"b") = 6 cycles db0 db1 da0 da1 db0 db1 dc0 dc1 low da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 note: l rc to the same bank must be satisfied. i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 desl wl = 4 wl = = 2 wl = 4 qs (output) wl = = 4 qs (output) db0 db1 da0 da1 db0 db1 dc0 dc1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 da0 da1 wl = 4 wl =
TC59LM836DKB-30,-33,-40 2004-08-27 39/65 rev 1.2 multiple bank write timing (cl = 6) note: l rc to the same bank must be satisfied. clk clk low ds (input) dq (input) bl = 2 wl = 5 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal wra lal wra address ua la ua la ua la bank add. bank "a" unidirectional ds/qs mode qs (output) wl = = 4 qs (output) unidirectional ds/free running qs mode wra lal lal wra lal wra lal wra ua la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 7 cycles i rc (bank"b") = 7 cycles db0 db1 da0 da1 db0 db1 low da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 desl wl = 5 wl = = 2 wl = 5 qs (output) wl = = 4 qs (output) db0 db1 da0 da1 db0 db1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 da0 da1 wl = 5 wl =
TC59LM836DKB-30,-33,-40 2004-08-27 40/65 rev 1.2 multiple bank read-write timing (bl = 2) cl k clk ds (input) cl = 4 i rbd = 2 cycles wl = 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 address bank add. unidirectional ds/qs mode cl = = 1 cycle i rwd = 2 cycles i wrd = = = 5 wl = 4 qs (output) cl = = 6 wl = 5 cl = = 4 wl = 3 cl = = 5 wl = 4 qs (output) cl = = 6 wl = 5 cl =
TC59LM836DKB-30,-33,-40 2004-08-27 41/65 rev 1.2 multiple bank read-write timing (bl = 4) cl k clk cl = 4 i rbd = 2 cycles wl = = = 1 cycle i rwd = 3 cycles i wrd = = = 5 wl = 4 qs (output) cl = = 6 wl = = = 1 cycle rda unidirectional ds/free running qs mode cl = 4 wl = = 4 qs (output) dq cl = 5 wl = 4 qs (output) cl = = 5 cl = = 6 ds (input) ds (input) ds (input) ds (input)
TC59LM836DKB-30,-33,-40 2004-08-27 42/65 rev 1.2 write with variable write length (vw) control (cl = 4) cl k clk ds (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal wra lal desl address ua la=#3 vw=all ua bank add. bank "a" bank "a" bl = 2, sequential mode desl la=#1 vw=1 vw0 = low vw1 = don't care vw0 = high vw1 = don't care dq (input) d0 d0 d1 lower address #3 #2 #1 ( #0 ) last one data is masked. ds (input) command wra lal wra lal desl address ua la=#3 vw=all ua bank add. bank "a" bank "a" bl = 4, sequential mode desl la=#1 vw=1 dq (input) d0 d0 d1 lower address #3 #0 #1 ( #2 )( #3 )( #0 ) last three data are masked. desl wra lal vw0 = high vw1 = low vw0 = high vw1 = high ua la=#2 vw=2 vw0 = low vw1 = high bank "a" d2 d3 d0 d1 #1 #2 last two data are masked. ( #0 )( #1 ) #2 #3 note: ds input must be continued till end of burst count even if some of laster data is masked.
TC59LM836DKB-30,-33,-40 2004-08-27 43/65 rev 1.2 power down timing (cl = 4, bl = 4) read cycle to power down mode clk clk 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 i pda t ih t is i pd = 2 cycle t pdex power down entry power down exit note: pd must be kept "high" level until end of burst data output. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied l pda cycles later. qs (output) command rda lal desl address ua ua desl rda or wra la l rc(min) , t refi(max) t qpdh ds (input) low hi-z cl = 4 hi-z dq (output) unidirectional ds/qs mode qs (output) ds (input) hi-z cl = 4 hi-z dq (output) unidirectional ds/free running qs mode pd q0 q1 q2 q3 q0 q1 q2 q3
TC59LM836DKB-30,-33,-40 2004-08-27 44/65 rev 1.2 power down timing (cl = 4, bl = 4) write cycle to power down mode clk clk 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 i pda t ih t is i pd = 2 cycle t pdex note: pd must be kept "high" level until wl+2 clock cycles from lal command. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied l pda cycles later. qs (output) command wra lal address ua ua desl rda or wra la l rc(min) , t refi(max) ds (input) low wl = 3 d0 d1 d2 d3 dq (input) unidirectional ds/qs mode qs (output) ds (input) dq (input) unidirectional ds/free running qs mode pd 2 clock cycles wl = 3 wl = 3 d0 d1 d2 d3 desl
TC59LM836DKB-30,-33,-40 2004-08-27 45/65 rev 1.2 mode register set timing (cl = 4, bl = 2) from read operation to mode register set operation. cl k clk ds (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rda lal rda mrs desl address ua valid (opcode) qs (output) i rsc = 7 cycles desl rd a or wr a la ua bank add. ba ba0="0" ba1="0" ba unidirectional ds/qs mode unidirectional ds/free running qs mode lal dq (output) ds (input) qs (output) dq (output) cl + bl/2 low q0 q1 q0 q1 note: minimum delay from lal following rda to rda of mrs operation is cl+bl/2 clock cycles. 15 la
TC59LM836DKB-30,-33,-40 2004-08-27 46/65 rev 1.2 mode register set timing (cl = 4, bl = 4) from write operation to mode register set operation. cl k clk ds (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 wra lal rda mrs desl address ua valid (opcode) qs (output) i rsc = 7 cycles desl rd a or wr a la ua bank add. ba ba0="0" ba1="0" ba unidirectional ds/qs mode unidirectional ds/free running qs mode low d0 d1 d2 d3 dq (input) ds (input) qs (output) d0 d1 d2 d3 dq (input) 15 wl+bl/2 la lal note: minimum delay from lal following wra to rda of mrs operation is wl+bl/2 clock cycles.
TC59LM836DKB-30,-33,-40 2004-08-27 47/65 rev 1.2 extended mode register set timing (cl = 4, bl = 2) from read operation to extended mode register set operation. cl k clk ds (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rda lal rda mrs desl address ua valid (opcode) qs (output) i rsc = 7 cycles desl rd a or wr a la ua bank add. ba ba0="1" ba1="0" ba unidirectional ds/qs mode unidirectional ds/free running qs mode dq (output) ds (input) qs (output) dq (output) cl + bl/2 low q0 q1 q0 q1 note: minimum delay from lal following rda to rda of emrs operation is cl+bl/2 clock cycles. when dq strobe mode is changed by emrs, qs output is invalid for l rsc period. dll switch in extended mode register must be set to enable mode for normal operation. dll lock-on time is needed after initial emrs operation. see power up sequence. 15 la lal
TC59LM836DKB-30,-33,-40 2004-08-27 48/65 rev 1.2 extended mode register set timing (cl = 4, bl = 4) from write operation to extende d mode register set operation. cl k clk ds (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 wra lal rda mrs desl address ua valid (opcode) qs (output) wl+bl/2 i rsc = 7 cycles desl rd a or wr a la ua bank add. ba ba0="1" ba1="0" ba unidirectional ds/qs mode unidirectional ds/free running qs mode low d0 d1 d2 d3 dq (input) ds (input) qs (output) d0 d1 d2 d3 dq (input) note: when dq strobe mode is changed by emrs, qs output is invalid for l rsc period. dll switch in extended mode register must be set to enable mode for normal operation. dll lock-on time is needed after initial emrs operation. see power up sequence. minimum delay from lal following wra to rda of emrs operation is wl+bl/2 clock cycles. 15 lal la
TC59LM836DKB-30,-33,-40 2004-08-27 49/65 rev 1.2 auto-refresh timing (cl = 4, bl = 4) cl k wra ref wra ref wra ref wra ref wra ref t 1 t 2 t 3 t 7 t 8 8 refresh cycle t refi = total time of 8 refresh cycle 8 t 1 + t 2 + t 3 + t 4 + t 5 + t 6 + t 7 + t 8 8 = t refi is specified to avoid partly concentrated current of refresh operation that is activated larger area than read / write operation. cl k clk qs (output) dq (output) 0 1 2 3 4 5 6 7 n ? 1n n + 1 n + 2 rda lal hi-z cl = 4 command i rc = 5 cycles desl rd a or wr a lal o r mrs or ref i rcd = 1 cycle note: in case of cl = 4, i refc must be meet 19 clock cycles. when the auto-refresh operation is performed, the sy nthetic average interval of auto-refresh command specified by t refi must be satisfied. t refi is average interval time in 8 refr esh cycles that is sampled randomly. wra ref i refc = 19 cycles i ras = 4 cycles i rcd = 1 cycle desl cl k clk qs (output) dq (output) rda lal hi-z hi-z cl = 4 command i rc = 5 cycles desl rd a or wr a lal o r mrs or ref i rcd = 1 cycle wra ref i refc = 19 cycles i ras = 4 cycles i rcd = 1 cycle desl unidirectional ds/qs mode unidirectional ds/free running qs mode bank, ua la bank,address bank, ua la bank,address low hi-z low q0 q1 q2 q3 q0 q1 q2 q3
TC59LM836DKB-30,-33,-40 2004-08-27 50/65 rev 1.2 self-refresh entry timing self-refresh exit timing notes: 1. is don?t care. 2. pd must be brought to "low" within the timing between t fpdl (min) and t fpdl (max) to self refresh mode. when pd is brought to "low" after l pdv , TC59LM836DKB perform auto refresh and enter power down mode. in case of pd fall between t fpdl (max) and l pdv , TC59LM836DKB will either entry self-refresh mode or power down mode after auto-refresh operation. 3. it is desirable that clock input is continued at least l ckd from ref command even though pd is brought to ?low? for self-refresh entry. 4. in case of self-refresh entry after write operation, the delay time from the lal command following wra to the ref command is write latency (wl)+2 clock cycles minimum. cl k clk qs (output) dq (output) 0 1 2 3 4 5 m ? 1mm + 1 wra ref qx hi-z command i rcd = 1 cycle i refc desl t fpdl (min) t fpdl (max) i pdv * 2 pd unidirectional ds/qs mode i ckd t qpdh auto refresh self refresh entry hi-z low notes: 1. is don?t care. 2. clock should be stable prior to pd = ?high? if clock input is suspended in self-refresh mode. 3. desl command must be asserted during i refc after pd is brought to ?high?. 4. i pda is defined from the fi rst clock rising edge after pd is brought to ?high?. 5. it is desirable that one auto-refresh command is issued just after self-refresh exit before any other operation. 6. any command (except read command) can be issued after i refc . 7. read command (rda + lal) can be issued after i lock . cl k clk qs (output) dq (output) 0 1 3 m ? 1mm + 1m + 2 command i lock t pdex i pd a = * 4 pd desl * 3 lal * 7 wra * 5 ref * 5 desl rda * 7 n ? 1nn + 1 p ? 1 p command (1st) * 6 command (2nd) * 6 i rcd = * 2 unidirectional ds/qs mode i refc i refc i rcd =
TC59LM836DKB-30,-33,-40 2004-08-27 51/65 rev 1.2 self-refresh entry timing self-refresh exit timing notes: 1. is don?t care. 2. clock should be stable prior to pd = ?high? if clock input is suspended in self-refresh mode. 3. desl command must be asserted during i refc after pd is brought to ?high?. 4. i pda is defined from the fi rst clock rising edge after pd is brought to ?high?. 5. it is desirable that one auto-refresh command is issued just after self-refresh exit before any other operation. 6. any command (except read command) can be issued after i refc . 7. read command (rda + lal) can be issued after i lock . 8. qs output is invalid until dll lock from self-refresh exit. cl k clk qs (output) dq (output) 0 1 3 m ? 1mm + 1m + 2 hi-z command i lock t pdex i pd a = 2 cycles * 4 pd desl * 3 lal * 7 wra * 5 ref * 5 desl rda * 7 n ? 1nn + 1 p ? 1 p command ( 1st ) * 6 command ( 2nd ) * 6 i rcd = * 2 unidirectional ds/free running qs mode i refc i refc i rcd = ? 1mm + 1 wra ref qx hi-z command i rcd = 1 cycle i refc desl t fpdl (min) t fpdl (max) i pdv * 2 pd unidirectional ds/free running qs mode i ckd t qpdh auto refresh self refresh entry
TC59LM836DKB-30,-33,-40 2004-08-27 52/65 rev 1.2 functional description network fcram tm the fcram tm is an acronym of fast cycle random access memory. the network fcram tm is competent to perform fast random core access, low latency and high-speed data transfer. pin functions clock inputs: clk & the clk and clk inputs are used as the refe rence for synchronous operation. clk is master clock input. the cs , fn and all address input signals are sampled on the crossing of the positive edge of clk and the negative edge of clk . the qs and dq output data are aligned to the crossing point of clk and clk . the timing reference point for the differential clock is when the clk and clk signals cross during a transition. power down: the pd input controls the entry to the power down or self-refresh modes. the pd input does not have a clock suspend function like a cke input of a standard sdrams, therefore it is illegal to bring pd pin into low state if any read or write operation is being performed. chip select & function control: & fn the cs and fn inputs are a control signal fo r forming the operation commands on fcram tm . each operation mode is decided by the combination of the two consecutive operat ion commands using the cs and fn inputs. bank addresses: ba0 & ba1 the ba0 and ba1 inputs are latched at the time of assertion of the rda or wra command and are selected the bank to be used for the operation. ba0 and ba1 also define which mode register is loaded during the mode register set command (mrs or emrs). ba0 ba1 bank #0 0 0 bank #1 1 0 bank #2 0 1 bank #3 1 1 address inputs: a0~a13 address inputs are used to access the arbitrary addr ess of the memory cell array within each bank. the upper addresses with bank addresses are latched at the rda or wra command and the lower addresses are latched at the lal command. the a0 to a13 inputs are also used for setting the data in the regular or extended mode register set cycle. upper address lower address TC59LM836DKB a0~a13 a0~a6 clk pd cs
TC59LM836DKB-30,-33,-40 2004-08-27 53/65 rev 1.2 data input/output: dq0~dq35 the input data of dq0 to dq35 are take n in synchronizing with the both ed ges of ds input signal. the output data of dq0 to dq35 are outputted synchronizin g with the both edges of qs output signal. data strobe: lds, uds, lqs, uqs method of data strobe is chosen by extended mode register. lds an d lqs are for dq0 to dq17. uds and uqs are for dq18 to dq35. (1) unidirectional ds / qs mode ds is input signal and qs is output signal. both edges of ds are used to sample all dqs at write operation. both edges of qs are used for trigger si gnal of all dqs at read operation. during write, auto-refresh and nop cycle, qs assert always ?low? level. qs is hi-z in self-refresh mode. (2) unidirectional ds / free running qs mode ds is input signal and qs is output signal. both edge of ds are used to sample all dqs at write operation. both edges of qs are used for trigger sign al of all dqs at read operation. qs assert always toggle signal except self-refresh mode. this strobe type is easy to use for pin to pin connect application. power supply: v dd , v ddq , v ss , v ssq v dd and v ss are power supply pins for memory core and peripheral circuits. v ddq and v ssq are power supply pins for the output buffer. reference voltage: v ref v ref is reference voltage for all input signals.
TC59LM836DKB-30,-33,-40 2004-08-27 54/65 rev 1.2 command functions and operations TC59LM836DKB are introduced the two consecutive command input method. th erefore, except for power down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. read operation (1st command + 2nd command = rda + lal) issuing the rda command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a read mode. when the lal command with lower addresses is issued at the next clock of the rda command, the data is read out sequentially synchronizing wi th the both edges of qs output signal (burst read operation). th e initial valid read data appears after cas latency from the issuing of the lal command. the valid data is outputted for a burst length. the cas latency, the burst length of read data and the burst type must be set in the mode register beforehand. the read operated bank goes back automatically to the idle state after l rc . write operation (1st command + 2nd command = wra + lal) issuing the wra command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a write mode. when the lal command with lower addresses is issued at the next clock of the wra command, the input data is latche d sequentially sync hronizing with the both edges of ds input signal (burst write operation). the data and ds inputs have to be asserted in keeping with clock input after cas latency-1 from the issuing of the lal command. th e ds has to be provided for a burst length. the cas latency and the burst type must be set in the mode register before hand. the write operated bank goes back automatically to the idle state after l rc . write burst length is controlle d by vw0 and vw1 inputs with lal command. see vw truth table. auto-refresh operation (1st command + 2nd command = wra + ref) TC59LM836DKB are required to refresh like a standard sdram. the auto-refresh operation is begun with the ref command following to the wra command. the auto-refresh mode can be effective only when all banks are in the idle state. in a point to notice, the write mo de started with the wra command is canceled by the ref command having gone into the next clock of the wra command instead of the lal command. the minimum period between the auto-refresh command and the next command is specified by l refc . however, about a synthetic average interval of auto-refresh command, it must be careful. in case of equally distributed refresh, auto-refresh command has to be issued within once for every 3.9 s by the maximum. in case of burst refresh or random distributed refresh, the av erage interval of eight consecutive auto-refresh commands has to be more than 400 ns always. in other words, the number of auto-refresh cycles that can be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. self-refresh operation (1st command + 2nd command = wra + ref with = ?l?) in case of self-refresh operation, refresh operation can be performed automatically by using an internal timer. when all banks are in the idle state and all outputs are in hi-z states, the TC59LM836DKB become self-refresh mode by issuing the self-refresh command. pd has to be brought to ?low? within t fpdl from the ref command following to the wra command for a self-refresh mode entry. in order to satisfy the refresh period, the self-refresh entry comman d should be asserted within 3.9 s after the latest auto-refresh command. once the device enters self-refresh mode, the desl command must be continued for l refc period. in addition, it is desirable that clock input is kept in l ckd period. the device is in self-refresh mode as long as pd held ?low?. during self-refresh mode, all input and output buffers are disabled except for pd , therefore the power dissipation lowers. regarding a self-refresh mode exit, pd has to be changed over from ?low? to ?high? along with the desl command, and the desl command has to be continuously issued in the number of clocks specified by l refc . the self-refresh exit function is asynchro nous operation. it is required that one auto-refresh command is issued to avoid the violation of the refresh period just after l refc from self-refresh exit. power down mode ( = ?l?) when all banks are in the idle state and dq outputs are in hi-z states, the TC59LM836DKB become power down mode by asserting pd is ?low?. when the devi ce enters the power down mode, all input and output buffers are disabled after specified time except for pd , clk, clk and qs. therefore, the power dissipation lowers. to exit the power down mode, pd has to be brought to ?high? and the desl command has to be issued for l pda cycle after pd goes high. the power down exit f unction is asynchronous operation. pd pd
TC59LM836DKB-30,-33,-40 2004-08-27 55/65 rev 1.2 mode register set (1st command + 2nd command = rda + mrs) when all banks are in the idle st ate, issuing the mrs command followi ng to the rda command can program the mode register. in a point to notice, the read mode started with the rda command is canceled by the mrs command having gone into the next clock of the rda co mmand instead of the lal command. the data to be set in the mode register is transferred using a0 to a13, ba0 and ba1 address inputs. the TC59LM836DKB have two mode registers. these are regular and extended mode register. the regular or extended mode register is chosen by ba0 and ba1 in the mrs co mmand. the regular mode register de signates the operation mode for a read or write cycle. the regular mode register has four function fields. the four fields are as follows: (r-1) burst length field to set the length of burst data (r-2) burst type field to designate the lower address access sequence in a burst cycle (r-3) cas latency field to set the access time in clock cycle (r-4) test mode field to use for supplier only. the extended mode register has three function fields. the three fields are as follows: (e-1) dll switch field to choose either dll enable or dll disable (e-2) output driver im pedance control field. (e-3) data strobe select once those fields in the mode register are set up, the register contents are maintained until the mode register is set up again by another mrs command or po wer supply is lost. the initial value of the regular or extended mode register after power-up is undefined, th erefore the mode register set command must be issued before proper operation. ? regular mode register/extended mode register change bits (ba0, ba1) these bits are used to choose eith er regular mrs or extended mrs ba1 ba0 mode register set 0 0 regular mrs 0 1 extended mrs 1 reserved regular mode register fields (r-1) burst length field (a2 to a0) this field specifies the data length for column access using the a2 to a0 pins and sets the burst length to be 2 or 4 words. a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 reserved 1 reserved (r-2) burst type field (a3) the burst type can be chosen interleave mode or se quential mode. when the a3 bit is ?0?, sequential mode is selected. when the a3 bit is ?1?, interlea ve mode is selected. both burst types support burst length of 2 and 4 words. a3 burst type 0 sequential 1 interleave
TC59LM836DKB-30,-33,-40 2004-08-27 56/65 rev 1.2 ? addressing sequence of sequential mode (a3) a column access is started from th e inputted lower address and is pe rformed by incrementing the lower address input to the device. addressing sequence for sequential mode data access address burst length data 0 n data 1 n + 1 data 2 n + 2 data 3 n + 3 2 words (address bits is la0) not carried from la0~la1 4 words (address bits is la1, la0) not carried from la1~la2 ? addressing sequence of interleave mode a column access is started from the inputted lower addr ess and is performed by inte rleaving the address bits in the sequence shown as the following. addressing sequence for interleave mode data access address burst length data 0 ??? a8 a7 a6 a5 a4 a3 a2 a1 a0 data 1 ??? a8 a7 a6 a5 a4 a3 a2 a1 0 a data 2 ??? a8 a7 a6 a5 a4 a3 a2 1 a a0 data 3 ??? a8 a7 a6 a5 a4 a3 a2 1 a 0 a 2 words 4 words (r-3) cas latency field (a6 to a4) this field specifies the number of clock cycles from the assertion of the lal command following the rda command to the first data read. the minimum value of cas latency depends on the frequency of clk. in a write mode, the place of clock that should input write data is cas latency cycles ? 1. a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 reserved (r-4) test mode field (a7) this bit is used to enter test mode for supplier on ly and must be set to ?0? for normal operation. (r-5) reserved field in the regular mode register ? reserved bits (a8 to a13) these bits are reserved for future operations. th ey must be set to ?0? for normal operation. cl k clk command qs dq data 0 data 1 data 2 data 3 rda lal cas latency = 4 (free running qs mode)
TC59LM836DKB-30,-33,-40 2004-08-27 57/65 rev 1.2 extended mode register fields (e-1) dll switch field (a0) this bit is used to enable dll. when the a0 bit is se t ?0?, dll is enabled. this bit must be set to ?0? for normal operation. (e-2) output driver impedanc e control field (a1 to a4) this field is used to choose outp ut driver strength. three types of driver strength are supported. qs and dq driver strength can be chosen separate ly. a2-a1 specified the dq driver strength. a4-a3 specified the qs driver strength. qs dq a4 a3 a2 a1 output driver impedance control 0 0 0 0 normal output driver 0 1 0 1 strong output driver 1 0 1 0 weak output driver 1 1 1 1 reserved (e-3) strobe select (a6 / a5) two types of data strobe are supported. this fiel d is used to choose the type of data strobe. (1) unidirectional ds/qs mode data strobe is separated ds for write strobe and qs for read strobe. ds is used to sample write data at write operation. qs is aligned with read data at read operation. (2) unidirectional ds/f ree running qs mode data strobe is separated ds for write strobe and qs for read strobe. ds is used to sample write data at write operat ion. qs is aligned with read data and always clocking. a6 a5 strobe select 0 0 reserved 0 1 reserved 1 0 unidirectional ds/qs mode 1 1 unidirectional ds/free running qs mode (e-4) reserved field (a7 to a13) these bits are reserved for future operations an d must be set to ?0? for normal operation.
TC59LM836DKB-30,-33,-40 2004-08-27 58/65 rev 1.2 boundary scan test acc ess port operations the TC59LM836DKB has a serial boundary scan test access port (tap) which is compatible with ieee standard 1149.1 ? 1990, but which does not implement all the functi ons required for 1149.1 ? 1990. tck must be tied to v ss or v dd to disable the tap when tap operation is not required. test access port signals symbol description tck test clock input all test access port inputs are sampl ed on the rising edge of tck. to disable the tap, tck must be tied to v ss or v dd . tms test mode select input the signal presented at tms is sampl ed on the rising edge of tck. this input is internally pulled up so as to rec ognize a floating input as a logical high (test-logic-reset). tdi test data input values presented at tdi are clocked in to the selected register on the rising edge of tck. this input is internally pulled up. this enables detection of when the tdi input to the board is open-circuit. tdo test data output tdo is the serial output for test instruct ions and data from the test logic. this output is controlled by the falling edge of tck. test access port registers register symbol length (bits) description instruction register ir [ 2 : 0 ] 3 the instruction register controls five states (extest, sample-z, sample, bypass, id code). test data register id register idr [ 31 : 0 ] 32 the register includes information on revision number, organization and toshiba id number. bypass register br 1 the register connects tdi and tdo. boundary scan register bsr [ 62 : 0 ] 63 the boundary scan register is comprised of boundary scan cells at each input and i/o pi n. the bscs are serially connected between tdi and tdo. tap controller instruction set ir2 ir1 ir0 instruction description 0 0 0 extest moves the preloaded data on to the output pins. samples the inputs connected to the bscs. 0 0 1 id code access id code. 0 1 0 sample ? z tristates the ram outputs and samples the inputs connected to the bscs. 0 1 1 reserved this instruction is reserved for future use. 1 0 0 sample samples the inputs connected to the bscs. load the sampled data at i/os to the parallel output of the bscs. does not affect ram operation. 1 0 1 reserved this instruction is reserved for future use. 1 1 0 reserved this instruction is reserved for future use. 1 1 1 bypass bypasses tdi and tdo using the bypass register. note: the first bit to be scanned into tdi is taken to be the least significant bit (ir0).
TC59LM836DKB-30,-33,-40 2004-08-27 59/65 rev 1.2 id register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 value 0 0 0 1 0 1 10 0 0 1 0000000010001 0 0 1 1 0001 content memory type toshiba id number fi xe d boundary scan order bit ball layout ball name bit ball layout ball name 0 u10 dq35 30 b10 dq0 1 u11 dq34 31 b3 dq17 2 t10 dq33 32 b2 dq16 3 t11 dq32 33 c3 dq15 4 r10 dq31 34 c2 dq14 5 r11 dq30 35 d3 dq13 6 p10 dq29 36 7 p11 dq28 37 d2 dq12 8 n10 dq27 38 e3 dq11 9 n11 uqs 39 e2 dq10 10 m3 a4 40 f3 dq9 11 m11 a3 41 f2 lds 12 l10 a2 42 g3 /clk 13 l11 a1 43 h3 clk 14 k10 a0 44 h2 /pd 15 k11 a10 45 j2 a12 16 j10 ba1 46 j3 a11 17 j11 ba0 47 k2 a9 18 g10 a13 48 k3 a8 19 g11 fn 49 l2 a7 20 h10 /cs 50 l3 a6 21 f11 lqs 51 m2 a5 22 f10 dq8 52 n2 uds 23 e11 dq7 53 n3 dq26 24 e10 dq6 54 p2 dq25 25 d11 dq5 55 p3 dq24 26 d10 dq4 56 r2 dq23 27 c11 dq3 57 28 c10 dq2 58 r3 dq22 29 b11 dq1 59 t2 dq21 60 t3 dq20 61 u2 dq19 62 u3 dq18
TC59LM836DKB-30,-33,-40 2004-08-27 60/65 rev 1.2 tap controller state diagram notes: 1. to enter the test-logic-reset state in order to initialize the device, keep tms high for at least five rising edges of the t ck. 2. the tdo output buffer is active only durin g shift operations (the shift-dr and shift- ir states) and is inactive (high-z) dur ing other states. test ? logic - reset tms = 1 run ? test / idle select ? dr - scan select ? ir - scan tms = 1 tms = 1 capture - dr capture - ir tms = 0 tms = 0 tms = 1 shift - dr shift - ir tms = 0 tms = 0 exit1 - dr exit1 - ir tms = 1 tms = 1 pause - dr pause - ir tms = 0 tms = 0 tms = 1 tms = 1 exit2 - dr exit2 - ir tms = 1 tms = 1 update - dr update - ir tms = 1 tms = 1 tms = 0 tms = 0 tms = 0 tms = 1 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 0 tms = 0 tms = 0 tms = 0 tms = 0
TC59LM836DKB-30,-33,-40 2004-08-27 61/65 rev 1.2 tap dc operating characteristics symbol parameter test condition min typ max unit i lo output leakage current (tdo pin) output deselected v out =0 to v dd ? 10 ? 10 a v in = 1.7v to v dd ? 20 ? 10 a i i input leakage current (tck, tms, tdi pins) v in = 0 to 0.7v ? 100 ? 10 a v ih input high voltage (tck, tms, tdi pins) ? v ref +0.4 ? v dd +0.2 v v il input low voltage (tck, tms, tdi pins) ? ? 0.1 ? v ref ? 0.4 v v oh output high voltage (tdo pin) i oh = ? 2 ma 1.5 ? v dd v v ol output low voltage (tdo pin) i ol = 2 ma ? ? 0.45 v ac characteristics ( v dd = 2.5v 0.125v, v ddq = 1.4v ~ 1.9v, t case = 0 ~ 85c ) TC59LM836DKB symbol parameter min max unit t thth tck cycle time 50 ? t thtl tck high pulse width 20 ? t tlth tck low pulse width 20 ? t mvth tms setup time to tck 10 ? t thmx tms hold time to tck 10 ? t cs capture setup time to tck 10 ? t ch capture hold time to tck 10 ? t dvth tdi setup time to tck 10 ? t thdx tdi hold time to tck 10 ? t tlqv output valid time from tck low ? 20 t tlqx output hold time from tck low 0 ? t tlqlz output low-z time from tck low 5 ? t tlqhz output high-z time from tck low ? 5 ns
TC59LM836DKB-30,-33,-40 2004-08-27 62/65 rev 1.2 tap ac test conditions parameter condition input pulse level 1.8v / 0.0v input pulse rise and fall time 2ns input timing measurement reference level 0.9v output timing measurement reference level 0.9v tap timing diagrams capture data t thth t tlth tms tc k t thtl t mvth t thmx t dvth t thdx t cs t ch tdi t tlqlz tdo t tlqx t tlqv t tlqhz output load tdo v l = 0.9v r l = 50 ? z = 50 ?
TC59LM836DKB-30,-33,-40 2004-08-27 63/65 rev 1.2 package dimensions 18.5 11.0 0.05 2.0 2.0 123456789101112 v u t r p n m l k j h g f e d c b a 0.75 0.8 0.5 0.05 0.2 s b 0.2 s a 0.15 4 index 0.08 s ab 0.5 1.0 1.1 b a 0.15min 1.2max 0.4 0.2 s 0.1 s s p-tfbga144-1119-0.80bz weight: 0.30g (typ.)
TC59LM836DKB-30,-33,-40 2004-08-27 64/65 rev 1.2 revision history ? rev.1.0 (feb. 26 ?2004) ? rev.1.1 (may. 25 ?2004) ? i dd6 spec changed from 10ma to 15ma (page 1, 7) ? v swing in ac test conditions changed from 0.7 v to 0.8 v (page 11) ? correct typo (page 54) ? rev.1.2 (aug. 27 ?2004) ? some notes in the page 8 moved to page 7 (page 7, 8). ? note 2 changed as below (page 7). before: these parameters depend on the output load ing. the specified values are obtained with the output open after: these parameters define the current between v dd and v ss . ? corrected typo (page 9, 14~18, 61, 62). ? t ck,max for ?-30? changed from 7.5 ns to 5.0 ns (page 9) ? package drawing minor change (page 63). ? package weight (0.30g) added (page 63)
TC59LM836DKB-30,-33,-40 2004-08-27 65/65 rev 1.2 ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of t he buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshi ba products specifications. also, pl ease keep in mind the precautions and conditions set forth in the ?handling guide for semicond uctor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signa l instruments, combusti on control instruments, medical instruments, all types of safety devices, et c.. unintended usage of toshiba products listed in this document shall be made at th e customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the down stream products which are prohibited to be produced and sold, under any law and regulations. 030619eb a restrictions on product use

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